1. Field of the Invention
This invention relates generally to data processors and more particularly to the timing of the instruction fetch and instruction execute phases of a microprocessor.
2. Description of the Prior Art
Data processors which execute a plurality of instructions stored in a memory are well known in the art. A typical prior art microprocessor includes a uni-directional address bus and a bidirectional data bus which are coupled to memories which store instructions and data operands. The microprocessor forces an address onto the address bus which corresponds to the location in memory of either an instruction word or a data word. The address is received by the memory and the addressed location is accessed. The accessed instruction or data word is then driven onto the data bus by the memory and transferred to the microprocessor during an instruction fetch or a data read cycle. Alternately, for a data write cycle, the microprocessor drives the data to be written onto the data bus and the data is transferred to the memory for storage. A typical instruction includes a first group of data bits often referred to as an opcode which specifies a particular operation to be performed on a data word. A second group of bits commonly referred to as an address field specifies the address of the particular data word or operand to be operated upon.
Data processors typically operate in a synchronous mode wherein each transfer of digital information is timed by various clock signals. The time required for the microprocessor to address an instruction in memory and receive the addressed instruction from memory is typically referred to as one machine cycle. Thus, a typical instruction requires two machine cycles, a first machine cycle to access or fetch the instruction from memory, and a second machine cycle to access the operand specified by the instruction. Since both machine cycles require the use of the data bus (the first to transmit the instruction and the second to transmit the operand), the next instruction may not be fetched until the subsequent or third machine cycle. Microprocessors have been disclosed which seek to overcome the limitations set forth above by overlapping fetch and execute cycles. However, these prior art microprocessors include several disadvantages, among which are the necessity for separate address and data busses for coupling the instruction memory to the microprocessor, and the necessity for two or more data busses for coupling an arithmetic-logic unit (ALU) to a memory used to store data operands. Therefore, it will be appreciated that a microprocessor which permits the overlap of fetch and execute cycles and which reduces the number of required digital busses is more efficient and represents a considerable improvement over the prior art.